In wired and wireless networking environments, performance of the network is monitored with the use of network analyzer devices. Network analyzer devices use counters to store information about network flows and other statistical measures related to traffic in a network. These counters are used for traffic policing, debugging failures, network monitoring and various other analysis and measurement functions.
When the number of counters in the device is very large, the cost and die-area to store the counters on-chip becomes prohibitive. Off-chip dynamic random access memory (DRAM) devices with caching algorithms can be used to solve this problem to allow for updating of the counters at the line-rate. However, using a standard DRAM device requires a higher input/output (I/O) bandwidth, a higher power to support the greater bandwidth and a long read-modify-write latency to support the exchanges between the memory device that stores the counters and the host device that updates the counters.